In high powered PCs and workstations, processors as well as cache, graphics subsystems and high speed communications equipment demand better performance from memories. In order to meet this demand, memory manufacturers offer an array of innovative fast memory chips for various applications. Even though the speed and bandwidth of DRAM (dynamic RAM) and SRAM (static RAM) has improved greatly, there are still differences in the speeds required by different processors.
A burst mode is provided for high speed random access of DRAM and SRAM. During the burst mode, k-bit data of an external column address for burst address access sequence is captured as a first address of a 2.sup.k -bit burst access. Additionally, k-1 burst addresses are generated automatically for the rest of burst access. According to this burst operation, since there is no need to receive external addresses in every cycle, the load of a system bus can be reduced. Also, since addresses are generated internally, a data rate is improved.
FIG. 1 is a block diagram showing a conventional synchronous burst SRAM device. The device is provided with a memory cell array 10, a column address buffer 14, a column decoder 20 and a column selection circuit 22. Buffer 14 receives an external column address and outputs an internal column address to decoder 20. The column decoder outputs a signal to column selection circuit 22 for selecting a column of the memory cell array.
The device also includes a sensing amplifying circuit 24 and a data output buffer 26 for the read operation. Additionally it includes a data input buffer 28 and a write drive circuit 30 for the write operation. A read/write control logic 32 generates signals SENij and WENij for controlling the read and write operations respectively.
The burst mode in the circuit of FIG. 1 is performed by a burst control logic 12, a burst counter 16, and a multiplexer 18. Burst control logic 12 receives external clock signal CLK and external mode signals ADV, ADSC, and ADSP, and generates burst control signals BC1 and BC2 accordingly. Burst counter 16 is constituted by a k-bit binary counter. This counter is cleared by burst control signal BC1. Burst control signal BC2 is used as a clock signal.
When external write enable signal WE is `H` (i.e., logical `1`), and processor address strobe signal ADSP is `L` (i.e., logical `0`), or when both signals WE and ADSP are `H` and signal ADSC is `L`, burst control logic 12 generates a burst control signal BC1 of `L` and a burst control signal BC2 of `H`. Then a k-bit column address signal from column address buffer 14 is loaded to burst counter 16. The k-bit column address signal thus loaded is used as a first address of the burst mode. Thus, a burst read cycle begins.
After that time, when signals WE, ADSP and ADSC are `H` and address advance signal ADV is `L`, the burst read cycle continues to be performed.
When signals WE and ADSC are `L` and signal ADSP is `H`, burst control logic 12 generates a burst control signal BC 1 of `L` and a burst control signal BC2 of `H`. A k-bit column address from column address buffer 14 is then loaded to burst counter 16. The address thus loaded is used as a first address of the burst mode. Thus, a burst write cycle begins.
After that time, when signals WE and ADV are `L` and signals ADSP and ADSC are `H`, the burst write cycle continues to be performed. Burst counter 16 sequentially generates the burst addresses in accordance with a predetermined sequence.
As described above, during the burst mode, a selection signal SEL of `H` is generated from burst control logic 12 to be applied to multiplexer 18. The output of burst counter 12 is delivered to column decoder circuit 20. Thus, during the burst mode, 2.sup.k m-bit column address signals from column address buffer 14 and multiplexer 18 are sequentially applied to column decoder circuit 20. Column decoder circuit 20 decodes the column address signals in order, and then generates column selection signals Y1.about.Yn one by one. Column selection circuit 22 selects columns of memory cell array 10 in response to column selection signals Y1.about.Yn.
During the burst read mode, the burst addresses are generated in accordance with the predetermined burst sequence. At the same time, outputs SENij of read/write control logic 32 are activated. Data stored in the memory cells of the selected columns are sequentially sensed, amplified, and stored in data output buffer 26. If the burst read sequence is completed, the bits stored in buffer 26 are delivered simultaneously to input/output line pairs 34.
During the burst write mode, the data on input/output data line pairs 34 is stored in a data input buffer 28. The burst addresses are then generated in accordance with the predetermined burst sequence. At the same time, outputs WENij of read/write control logic 32 are activated. Thus, the data stored in buffer 28 is written sequentially in the memory cells of the selected columns.
On the other hand, when signals ADSP, ADSC and ADV are `H`, the burst mode is suspended. Burst control logic 12 then generates a burst control signal BC1 of `H` and a burst control signal BC2 of `L`. Thus, column address buffer 14 receives new external column addresses, and burst counter 16 is cleared. Burst control logic 12 also generates a selection signal SEL of `L`. This causes a k-bit signal from buffer 14 to be delivered to column decoder circuit 20 by multiplexer 18. In this case, the m-bit internal address signal from buffer 14 is provided directly to column decoder circuit 20.
In the conventional burst SRAM device of FIG. 1, since memory cells have to be accessed through column decoder circuit 20, a high speed burst counter logic must be used. If it is, an internal address access time such as a burst address access time, limits the speed of operation.